6  Exception and Interrupt Processing

6.1  Hardware Exception Sources

6.1.1  System Reset Interrupt

6.1.2  Machine Check Interrupt

6.1.3  DSI Interrupt

6.1.4  ISI Interrupt

6.1.5  External Interrupt

6.1.5.1   Setup

• set corresponding bit(s) in PI Interrupt Mask Register (0xcc003004)
• enable external Interrupts in the Machine State Register

6.1.5.2   Handling

• check PI Interrupt Cause Register (0xcc003000) for flags
• acknowledge by setting corresponding bits in PI Interrupt Cause Register (0xcc003000)
• handle different interrupt sources

6.1.6  Alignment Interrupt

6.1.7  Program Interrupt

6.1.8  FP unavailable Interrupt

6.1.9  Decrementer Interrupt

6.1.10  System Call Interrupt

6.1.11  Trace Interrupt

6.1.12  Performance Monitor Interrupt

6.1.13  IABR Interrupt

6.1.14  Thermal Interrupt

6.2  External Interrupt Sources

6.2.1  HSP - High Speed Port

6.2.1.1   TX Mailbox Interrupt

6.2.1.2   RX Mailbox Interrupt

6.2.1.3   ID Interrupt

6.2.2  Debug

6.2.3  CP - Command Processor

6.2.3.1   FIFO underflow

• setup CP FIFO low watermark
• set bit 1 of CP interrupt status register (0xcc000002) to enable

• clear bit 3 of CP interrupt status register (0xcc000002) to acknowledge

6.2.3.2   FIFO overflow

• setup CP FIFO high watermark
• set bit 0 of CP interrupt status register (0xcc000002) to enable

• clear bit 2 of CP interrupt status register (0xcc000002) to acknowledge

6.2.4  PE - Pixel Engine Finished

6.2.4.1   setup

• set bit 1 in PE Interrupt status register (0xcc001000a)

6.2.4.2   handling

• set bit 3 in PE Interrupt status register (0xcc001000a) to acknowledge the interrupt

6.2.5  PE - Pixel Engine Token

6.2.5.1   setup

• set bit 0 in PE Interrupt status register (0xcc001000a)

6.2.5.2   handling

• check PE Token Register (0xCC00000E) for the token that triggered the interrupt.
• set bit 2 in PE Interrupt status register (0xcc001000a) to acknowledge the interrupt

6.2.6  VI - Video Interface

6.2.6.1   Setup

• setup desired position of the interrupt
• set enable bit in Display Interrupt Register (0xcc002030) (0xcc002034) (0xcc002038) (0xcc00203c)

6.2.6.2   Handling

• clear Status bit in Display Interrupt Register (0xcc002030) (0xcc002034) (0xcc002038) (0xcc00203c) to acknowledge the interrupt.

6.2.7  Memory Interface

6.2.7.1   protection fault

• clear (0xCC004020)
• setup the regions in (0xCC004000)(0xCC004004)(0xCC004008) (0xCC00400c)
• setup type of protection in (0xCC004010)
• enable protecting of regions in irq mask (0xCC00401c)

• clear (0xCC004020)
• read status bits from (0xCC00401e) to check what region triggered the protection fault
• set status bits in (0xCC00401e) to acknowledge the interrupt
• read the address that triggered the protection fault from (0xCC004022) and (0xCC004024)

6.2.8  DSP Interface

6.2.8.1   Audio DMA finished

• set bit 4 of DSP Control Register (0xcc00500a)

• set bit 3 of DSP Control Register (0xcc00500a) to acknowledge the interrupt.

6.2.8.2   ARAM transfer complete

6.2.8.3   DSP

6.2.9  Audio Streaming Interface

6.2.10  EXI

6.2.10.2   Ethernet Adapter (EXIIRQ channel 2)

• check command register 3 (irq status) for the exact source (MX chip, killing irq,cmd error, challenge/response request, challange/response status)
• if from MX chip, check register 8 and 9 for the exact cause

• To check whether the device has been inserted or removed, check the EXICPR[EXT] bit.

6.2.11  Serial Interface

6.2.12  DVD Interface

6.2.12.1   Break Complete

6.2.12.2   DMA finished

6.2.12.3   Device Error

6.2.12.4   Cover State changed

6.2.13  Reset Button

6.2.13.1   setup

• no further setup required

6.2.13.2   handling

• nothing special required, its however recommended to clear the PI Interrupt Mask to avoid multiple interrupts.

6.2.14  Error